1. Course: Analog Circuit Design Time schedule: Mo 11.00-13.00 We14.00-16.00 Th16.00-18.00 Office hours: We 16.00-18.00 Exams: Feb. (2), Jun.-Jul. (2), Sep. (2) Oral examination Additional course material: ftp://ftp.dii.unisi.it/pub/users/vignoli/Analog_Circuit_Design

2. Course: Analog Circuit Design Time schedule: Mo 11.00-13.00 11.15 – 12.45 We14.00-16.00 14.30 – 16.00 Th16.00-18.00 16.00 – 17.30 Office hours: We 16.00-18.00 Exams: Feb. (2), Jun.-Jul. (2), Sep. (2) Oral examination Additional course material: ftp://ftp.dii.unisi.it/pub/users/vignoli/Analog_Circuit_Design

3. References: F. Maloberti Analog Design for CMOS VLSI Systems Kluwer 2001 J. Millman, C. Halkias Integrated Electronics: Analog and Digital Circuit and Systems McGraw-Hill 1972 R. Spencer, M. Ghausi Introduction to Electronic Circuit Design Prentice Hall 2003 P. Gray, R Meyer Analysis and Design of Analog Integrated Circuits (3rd ed.) Wiley 1993 M.S. Tyagi Introduction to Semiconductor Material and Devices Wiley 1991

7. MATERIALS: electric behavior semiconductorInsulatorconductor

8. In semiconductors E F is in the Band-Gap SEMICONDUCTORS: electric behavior Fermi-Dirac distribution: occupation probability for the energy level E

9. N C is the number of available states (per cm -3 ) in the conduction band where N e (E) is Energetic State Density function in the material. Intrinsic Semiconductors: free carriers

10. DOPING The Fermi energy moves with doping E F n-type E F p-type T effect ACCEPTOR DONOR

13. PHOTOLITOGRAPHY Photoresist spin.-coating Thick film: 1 mm EXPOSITION: The mask is transferred to the photoresist Uv - X-ray

14. The photoresist chemically reacts and dissolves in the developing solution, only on the parts that were not masked during exposure (positive method). Development is performed with an alkaline developing solution. After the development, photoresist is left on the wafer surface in the shape of the mask pattern. Masked photoresist solvents remove exposed (unexposed) resist Etching removes material from wafer surface where resist has been removed

15. Wet etching Dry etching

18. Also PVD

19. Materials: Si substrate Monocrystalline silicon is produced from purified polycrystalline silicon by “pulling” an ingot –polysilicon is melted using radio frequency induction heaters –“seed crystal” of monocrystalline silicon is dipped into melt –silicon grows around structure of seed as seed is slowly withdrawn Sawed into wafers about 600 microns thick –only a few microns are actually used for IC devices –then etched, polished, and cleaned –stacked in carriers

21. Single crystal silicon – SCS –Anisotropic crystal –Semiconductor, great heat conductor Silicon dioxide is created by interaction between silicon and oxygen or water vapor –Si + O 2 = SiO 2 or Si + 2H 2 O = SiO 2 + 2H 2 –Excellent thermal and electrical insulator –protects surface from contaminants –forms insulating layer between conductors –forms barrier to dopants during diffusion or ion implantation –grows above and into silicon surface –Thermal oxide, LTO, PSG: different names for different deposition conditions and methods Polycrystalline silicon – polysilicon –Mostly isotropic material –Semiconductor –also a conductor, but with much more resistance than metal or diffused layers –created when silicon is epitaxially grown on SiO 2 –commonly used (heavily doped) for gate connections in most MOS processes Silicon nitride – Si 3 N 4 –Excellent electrical insulator Aluminum – Al –Metal – excellent thermal and electrical conductor Materials

22. EFFECT OF FLATBAND VOLTAGE V FB (V FB < 0)

23. V GB = 0

24. GATE Polisilicon OXIDE SiO 2 SUBSTRATE P-type Si SUBSTRATE CONTACT Polisilicon - - Space charge regions x -t OX 0 xDxD x 0 xDxD Potential V GB -V FB -V FB V GB V OX Φ s (0) + V OX

25. STRONG INVERSION CONDITION

27. SMALL SIGNAL EQUIVALENT CIRCUIT OF A MOS TRANSISTOR

28. MOS TRANSISTOR LAYOUT SOURCE AND DRAIN PARASITIC RESISTANCES SOURCE AND DRAIN PARASITIC CAPACITANCES MATCHING

29. SOURCE AND DRAIN PARASITIC RESISTANCES

30. SOURCE AND DRAIN PARASITIC CAPACITANCES

31. MATCHING You must avoid: DDSS Use always the same MOS orientation in your layout: silicon is anisotropic

32. MATCHING 1 23

33. 1 23

35. DESIGN RULES Geometrical recommendations due to the limited accuracy of the technology (mask alignment, lateral diffusion, etching undercut, optical resolution…) Design Kit: design rules + Spice models and technology features

36. INTEGRATED RESISTORS 1

37. DIFFERENT SOLUTIONS (a) INTEGRATED RESISTORS 2

38. POLYSILICON RESISTORS Lower coupling with substrate Up to two shieldings Top shielding (from noisy metal lines, package coupling….) DIFFERENT SOLUTIONS (b) INTEGRATED RESISTORS 3

40. Poor absolute accuracy (20-40% - large parameter drift) Good matching (ratio) accuracy (0.1-0.2% - it depends on local parameter variations) INTEGRATED RESISTORS 4 FACTORS AFFECTING ACCURACY

41. Poor absolute accuracy (20-40% - large parameter drift) Good matching (ratio) accuracy (0.1-0.2% - it depends on local parameter variations) INTEGRATED RESISTORS 4 FACTORS AFFECTING ACCURACY

42. Poor absolute accuracy (20-40% - large parameter drift) Good matching (ratio) accuracy (0.1-0.2% - it depends on local parameter variations) INTEGRATED RESISTORS 4 FACTORS AFFECTING ACCURACY

43. Poor absolute accuracy (20-40% - large parameter drift) Good matching (ratio) accuracy (0.1-0.2% - it depends on local parameter variations) INTEGRATED RESISTORS 4 FACTORS AFFECTING ACCURACY

44. Design Guidelines (a) INTEGRATED RESISTORS 5

45. Design Guidelines (b) INTEGRATED RESISTORS 6

46. Design Guidelines (c) INTEGRATED RESISTORS 7

47. INTEGRATED CAPACITORS 1

48. INTEGRATED CAPACITORS 2

49. tox ≤ 10 nm ε r (SiO 2 )=3.8 C OX ~ 3.36 fF/μm 2 C OX INTEGRATED CAPACITORS 3

50. INTEGRATED CAPACITORS 4

51. INTEGRATED CAPACITORS 5

52. A’ = W’L’  WL – 2 (L+W)Δx = A – P Δx = A (1 - Δx P/A) The relative reduction of A remains constant, given Δx, if the ratio P/A is constant (matched elements) The fringe effect reduces the capacitance at the plate boundary proportionally to tox P/A -> (L, W >> tox) Effect of the thick oxides at the plate boundary INTEGRATED CAPACITORS 6

53. Layout examples for poly1-poly2 capacitors INTEGRATED CAPACITORS: LAYOUT 1

54. Matching: capacitors with integer ratio Shielding (well and/or metal) INTEGRATED CAPACITORS: LAYOUT 2

55. Matching: capacitors with not-integer ratio squared capacitors with area C 1 = L 2 [C2/C1][C2/C1] 1 rectangular capacitor with area C k= W k L k = ( C 2 /C 1 - ) C 1 All the capacitors with constant P/A   L 2 /4L=L/4=L k W k /2(L k + W k )  C k /C 1 =L k W k /L 2 [C2/C1][C2/C1] INTEGRATED CAPACITORS: LAYOUT 3

56. PASSIVE COMPONENTS: CAPACITORS – Design Guidelines