1. 1 Chapter 5: Datapath and Control (Part 2) CS 447 Jason Bakos

2. 2 Building a Datapath Which components do we need for the A/L, load, and branch classes of MIPS instructions? –First, we need a memory to hold our instructions Assume it has an address input, data output, and a MemRead and MemWrite control signals –A Program Counter (PC) register to hold the address of the next instruction Typical register (clk, en, rst, D, and Q) –ALU (the one we built in Chap. 4) A, B, ALUOp, and Out –Register file Dual-port (ReadAddr1, ReadAddr2, WriteReg, WriteData, RegWrite, ReadData1, ReadData2) –Instruction Register Like the PC, but holds the current instruction word

3. 3 Building a Datapath

4. 4 Datapaths Assuming our instruction is already fetched, using our components we need to build datapaths for the following: –PC=PC+4 –Executing A/L R-type instruction and writing back result –Executing load/store effective address calculation We need a sign extender for this –Computing a branch target address and determining whether or not a branch should be taken (for beq) We need a sign extender and a 2-bit shifter for this

5. 5 Datapaths PC+4 datapathR-type A/L datapath

6. 6 Datapaths Load/Store Datapath

7. 7 Datapaths Branch (beq) Datapath

8. 8 Simple CPU Implementation We want to implement the simplest possible implementation of our MIPS subset of instructions –lw/sw –beq –add, sub, and, or, and slt

9. 9 Combining Datapaths Let’s combine the datapaths that we looked at into a single datapath Let’s assume that we want to execute all our instructions in a single clock cycle –This means that we can only use each datapath component once per instruction We need a separate instruction and data memory We may need to duplicate some components (but we can share components across different instruction types) We need multiplexors for this

10. 10 Integrated Datapaths Here we combine all our datapaths We also add our fetch hardware Next we’ll need a control unit to assert the control signals

11. 11 Control Signals Recall the ALU control table… Let’s create a small control “lookup table” for the ALU... ALU OperationFunction 000and 001or 010add 110subtract 111set on less than

12. 12 Control Signals InstructionALUOpFuncFieldDesired ALU Action ALU Control Input LW00XXXXXXadd010 SW00XXXXXXadd010 BEQ01XXXXXXsubtract110 R-type (add)10100000add010 R-type (sub)10100010subtract110 R-type (and)10100100and000 R-type (or)10100101or001 R-type (slt)10101010slt111 Note that ALUOp will come from the main control unit

13. 13 Designing the Main Control Unit First, let’s take a look at all our current control signals and their effect... Signal Name Effect when deasserted Effect when asserted RegDst Register destination comes from rt field (20-16) Register destination comes from the rd field (15-11) RegWrite NoneA register is written to ALUSrc The second ALU operand comes from register file (2) The second ALU operand is the sign-extended register immediate PCSrc The PC is replaced by the output of the adder (PC+4) The PC is replaced by the adder that computes branch target MemRead NoneData memory read MemWrite NoneData memory written MemtoReg The value fed to the register file comes from the ALU The value fed to the register file comes from data memory

14. 14 CPU with Control Unit

15. 15 R-type Control For an R-type instruction, let’s decide what needs to be done (note this is done in parallel) –Fetch instruction and increment PC by 4 –Read two registers –ALU does computation –Result is written back to register file

16. 16 Load/Store Control Let’s decide what needs to be done for a lw instruction –Fetch/increment PC –Read base register from reg. file –ALU computes effective address (base+offset) –Data from memory is written back to register file

17. 17 Branch-on-Equal Control Finally, let’s decide what needs to be done in order to perform the beq instruction –Fetch/increment PC –Read two registers –ALU subtracts –ALU computes effective branch target (PC+offset*4) –Zero result from ALU decides if we should write the new value to the PC

18. 18 Control Signals InstructionRegDstALUSrcMemto Reg RegWriteMem Read Mem Write BranchALU Op1 ALU Op2 R-type100100010 lw011110000 swX1X001000 beqX0X000101

19. 19 Control Next time we’ll find out why a single- cycle CPU like this is not practical –We need a FSM to handle control in order to reuse components during a single instruction execution