1. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock APPLIED VLSI DESIGN The third design of Robert Gubitz

2. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 2 Stage 2 design

3. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Changes since Stage 2 Replace the remaining Carry-Save-Array multipliers with Wallace Tree multipliers Use term sharing for the multipliers Replace Ripple-Carry adders with Carry-Skip look-ahead adders Added additional pipeline stages

4. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Term Sharing Precalculate coefficient*color and share between multipliers Y: 001001_10010001_01101001 010010_11001000_10110100 000011_10100101_11100011 Cb: 000101_01100110_01001001 001010_10011001_10110111 001111_11111111_11111111 – replaced with shifter Cr: 001111_11111111_11111111 -- replaced with shifter 001101_01100101_11100100 000010_10011010_00011100

5. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Carry-Skip-Lookahead-Adder Ripple-Carry adders work only for FPGA  replacement with faster adders combination of look-ahead and skip-logic

6. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Resulting Design

7. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Finding Sweet-Spot Adjust desired leakage power to very low value Synthesize for multiple frequencies and make a diagram to find metric‘s theoretical sweet spot Slide 7 Sweet-Spot

8. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 8 Results – Synthesis First ASIC approach Frequency (in MHz) 120 N cycles 41376 t Op (in s) 3,448 * 10 -4 P leak (in nW) 99,8089 E Avg 0,249701 Metric5,3579 * 10 -13 Ws

9. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock THANK YOU FOR YOUR ATTENTION