1. l i a b l eh kC o m p u t i n gL a b o r a t o r y Modeling TSV Open Defects in 3D-Stacked DRAM Li Jiang †, Liu Yuxi †, Lian Duan ‡, Yuan Xie ‡, and Qiang Xu † Presenter: Qiang Xu † CUhk REliable Computing Laboratory Department of Computer Science & Engineering The Chinese University of Hong Kong ‡ Department of Computer Science & Engineering Pennsylvania State University, USA

2. Purpose New test challenges for 3D-stacked DRAM Massive amount of TSVs that are prone to open defects and coupling noises Conduct extensive simulation to study the faulty behavior of TSV open defects

3. Outline Introduction Motivation Simulation Methodology Simulation Results Conclusion

4. Why 3D-Stacked DRAM? Ever-increasing performance gap between processor and memory Excessive latency Limited bandwidth 3D-stacking is a promising solution to tackle this “Memory Wall” problem

5. 3D-Stacked DRAM is Already Here … NEC: 4Gb, 8 Layers 4 Gbit density Interposer Peripherals 3 Gbps/pin 8 strata TSVSamSung: 8Gb, 4 Layers PCB TSV DRAM I/O Buffer RD/WR

6. “True” 3D-Stacked DRAM Much better performance when compared to using TSVs only for buses TSV density is extremely high Loh ISCA’08 One rank in multiple layers Separate peripheral logic layer

7. Motivation TSVs are prone to open defects Contamination O 2 trapped in bonding surface Miss Alignment/dislocation Mechanical failures in TSVs Contact resistances M. Kawano, et al. IEDM’06 Voids during filling

8. Motivation Separation (um) C vc (fF)C gc (fF) 11.160.87 30.600.97 50.421.05 70.311.04 90.251.04 I. Savidis et.al. ISCAS08 Capacitive coupling between adjacent TSVs is NOT negligible!

9. 3D Memory Model Write Operation Read Operation Enable 0 1 1 0 1 0 1 0 1 0

10. Simulation Setup SPICE simulation Open defect represented by a very large resistance Vdd 1.8v, Vth 0.6v Coupling capacitance is set according to previous work

11. Simulation Schematic for Wordline Open R open Vsig WL 1 X WL 0 WL 2

12. Wordline Open Access the open wordline Access the neighboring wordline of open wordline Vary wordline load capacitance Vary trapped charges in pass-transistor

13. Wordline Write No Access to open wordline Access its neighboring wordline of the (WL 1 ) Write 1 to Cell 4 Write 0 to Cell 4 Strong write 0 (1w0),Weak write 1 (0w1) 10 0 01 1

14. Wordline Read Multiple Access Two scenarios: Cell in the same bitline Cell in Complemented bitline C7C7 C4C4 0 0 1 11 0 0 1 0 00 (C load =200fF) (V trap >0.7V)(V trap >1V)

15. Simulation Schematic for bitline Open R open SE Aggressor Victim

16. Bitline Read Access WL 0,No Error C 1  BL i  BL i Access WL 1, C 6  BL i+1  BL i C 4  BL i-1  BL i-1  BL i Driving force determine the output of open bitline 00 V ref 10

17. Coupling from Multiple Layer More complicated coupling effect Interference from other layer

18. Fault Modeling No Access Multiple Access Coupling by neighbor

19. Conclusion The massive amount of TSVs used in “True” 3D-stacked DRAM are prone to open defects and coupling noises We model the faulty behavior of open TSVs and show their effects through extensive simulation

20. Thank you for your attention !