1. Univ. of TehranIntroduction to Computer Network1 An Introduction to Computer Networks University of Tehran Dept. of EE and Computer Engineering By: Dr. Nasser Yazdani Lecture 7: Switch fabric design

2. Univ. of TehranIntroduction to Computer Network2 Outline Introduction What are switches? Basic concepts Design factors Performance factors Functional requirements Design architectures

3. Univ. of TehranIntroduction to Computer Network3 Switches A means to create connectivity Why switching? Efficient utilization of resources Store and forward scheme incoming linksoutgoing links Node Memory

4. Univ. of TehranIntroduction to Computer Network4 Switched Network A network consisting of switching elements. Hosts can connect to the network directly or through LANs. n links Switches Switched Network

5. Univ. of TehranIntroduction to Computer Network5 Basic concepts An ideal switch: route all incoming packet to their requested outputs with the following conditions: No loss Minimum delay Preserving order Output contention: At least two input goes to one output. we need buffer and queuing (how much?) Congestion: no buffer space left. Drop packet

6. Univ. of TehranIntroduction to Computer Network6 Design Factors Throughput Max throughput- N x line speed where N is the # of input line Ave throughput – At random is %60. Packet per second (PPS)- # of packets switched per second Throughput depends on the traffic. Quality of service: Ave delay of cells Jitter Reliability in switching cells.

7. Univ. of TehranIntroduction to Computer Network7 Design Factors Scalability: how the architecture scale, linear? Square? Regarding the speed of input line Regarding the # of input port. Cost: # of logic gates Memory Bandwidth or # of pines

8. Univ. of TehranIntroduction to Computer Network8 Performance Factors Traffic pattern: Packet arrival rate. Destination distribution Addressing and operation: Unicast or multicast operation Priority- Differentiation among packets

9. Univ. of TehranIntroduction to Computer Network9 Functional requirement User plane: Data is carried transparently Header are processed and VPI/VCI is used for routing. LC IPP SFC OPP LC 0 0 … … Central unit

10. Univ. of TehranIntroduction to Computer Network10 Functional requirement Cntrl plane: Signaling Identified by VPI/VCI, 5/0 is for call admission. May use SFC for transporting ctrl packets. LC IPP SFC OPP LC … … IPP+ SFC+ OPP Store and forward system. CAC CAC- Call Admission Control

11. Univ. of TehranIntroduction to Computer Network11 Functional requirement Management plane: System Management (SM) must handle management cell. Should support Network wide operations. May use SFC for transporting management cells. LC IPP SFC OPP LC … … SM

12. Univ. of TehranIntroduction to Computer Network12 Workstation-Based switch Aggregate bandwidth 1/2 of the I/O bus bandwidth capacity shared among all hosts connected to switch example: 800Mbps bus can support 8 T3 ports CPU Main memory I/O bus Interface 1 Interface 2 Interface 3 Packets-per-second must be able to switch small packets 100,000 packets-per- second is achievable e.g., 64-byte packets implies 51.2Mbps

13. Univ. of TehranIntroduction to Computer Network13 Route Table CPU Buffer Memory Line Interface MAC Line Interface MAC Line Interface MAC Typically < 0.5Gbps aggregate capacity Limited by rate of shared memory Shared Backplane Line Interface CPU Memory Slide by Nick McKeown ArchitecturesArchitectures: First Generation

14. Univ. of TehranIntroduction to Computer Network14 Route Table CPU Line Card Buffer Memory Line Card MAC Buffer Memory Line Card MAC Buffer Memory Fwding Cache Fwding Cache Fwding Cache MAC Buffer Memory Typically < 5Gb/s aggregate capacity Limited by shared bus Slide by Nick McKeown ArchitecturesArchitectures: Second Generation

15. Univ. of TehranIntroduction to Computer Network15 Line Card MAC Local Buffer Memory CPU Card Line Card MAC Local Buffer Memory Switched Backplane Line Interface CPU Memory Fwding Table Routing Table Fwding Table Typically < 50Gbps aggregate capacity Slide by Nick McKeown ArchitecturesArchitectures: Third Generation

16. Univ. of TehranIntroduction to Computer Network16 Switch fabric design Shared Media Bus Architecture Shared buffer Space division Cross bar architecture Combination of above Note: Self-routing is to direct packet inside the fabric.

17. Univ. of TehranIntroduction to Computer Network17 Bus Architecture IPP puts cells on bus OPP buffer cells Control Processor (CP) exchanges control messages configures connections Bus interconnects various components. » In nonblocking systems bandwidth is equal to sum of external link bandwidths; » bus width must increase with number of links » capacitive loading reduces clock rate as number of links grows

18. Univ. of TehranIntroduction to Computer Network18 Divided Bus with Knockout Concentrators Split bus into n “minibuses” with w  n wires each Each minibus driven by just one IPP. cuts capacitive loading in half adding fanout components allows higher clock frequencies OPPs concentrate n minibuses onto L<n outputs (optional) OPPs must each be able to buffer up to L cells in parallel Parallel reception complicates control somewhat Concentration reduces required OPP memory bandwidth IPP w wnwn OPPs

19. Univ. of TehranIntroduction to Computer Network19 Knockout Switch Concentrator select l of n packets Complexity: n 2 D 1234 Outputs Inputs D D D DD D D DD D D D D

20. Univ. of TehranIntroduction to Computer Network20 Shared Buffer Switches For switches with 10 or more links, can reduce required memory by up to an order of magnitude. n Queues are rarely full, then, memory for queues is unused mostly n With shared memory, we can achieve same performance level with less memory. n Requires a central memory with bandwidth equal to twice the external link bandwidth. n Per output or per flow queues typically implemented as linked lists.

21. Univ. of TehranIntroduction to Computer Network21 crossbar Architecture crossbar allows multiple cells to pass in parallel to distinct outputs » use of point-to-point transmission eliminates capacitive loading at circuit board level » parallelism reduces data path width at IPPs, OPPs control circuit arbitrates access to outputs retains quadratic complexity, but concentrates it within chip, reducing system cost IPP OPP

22. Univ. of TehranIntroduction to Computer Network22 ExamplesExamples: Cisco GSR - 12416 WAN Router – Large throughput; SONET links Up to 16 line cards at 10 Gbps each Crossbar Fabric Line Cards: 1-port OC-192c 4-port OC48c Many others (ATM, Ethernet, …) Cisco GSR 12416 6ft 19 ” 2ft