2. OSINITSetinterruptvectors: Time-sliceclockSCHEDULER SoftwareinterruptOSSERVICES KeyboardinterruptsIOData... OSSERVICESExaminestacktodeterminerequestedoperation. Callappropriateroutine. SCHEDULERSaveprogramstate. Selectarunnableprocess. Restoresavedcontextofnewprocess. PushnewvaluesforPSandPConstack. Returnfrominterrupt. (a) OS initialization, services, and scheduler IOINITSetprocessstatustoBlocked. Initializememorybufferaddresspointerandcounter. Calldevicedrivertoinitializedevice andenableinterruptsinthedeviceinterface. Returnfromsubroutine. IODATAPolldevicestodeterminesourceofinterrupt. Callappropriatedriver. IfEND=1,thensetprocessstatustoRunnable. Returnfrominterrupt. (b) I/O routines KBDINITEnableinterrupts. Returnfromsubroutine. KBDDATACheckdevicestatus. Ifready,thentransfercharacter. Ifcharacter=CR,then{setEND=1;Disableinterrupts } elsesetEND=0. Returnfromsubroutine. (c) Keyboard driver Figure 4.10. A few operating system routines.   

4. Mainprogram MOVR0,#0 STRR0,EOLClearEOLflag. ADRR1,DATAINLoadaddressofRegisterDATAIN. LDRBR0,[R1,#3]Get contentsofCONTROLregister. ORRR0,R0,#4SetbitKENinregisterCONTROL STRBR0,[R1,#3]toenablekeyboardinterrupts. MOVR0,#&50EnableIRQinterruptsinprocessor MSRCPSR,R0andswitchtousermode.... IR Q Interrupt-serviceroutine READSTMFDR13!,{ R0  R2,R14 irq}SaveR0,R1,andR14irqonthestack. ADRR1,DATAINLoadaddressof register DATAIN. LDRBR0,[R1]Getinputcharacter. LDRR2,PNTRLoadpointervalue. STRBR0,[R2],#1Storecharacterandincrementpointer. STRR2,PNTRUpdatepointervalueinthememory. CMPBR0,#&0DCheckifCarriageReturn. LDMNEFDR13!,{ R0  R2,R14 irq}Ifnot,restoreregisters SUBNESPC,R14irq,#4andreturn. LDRB R0,[R1,#3] OtherwisegetCONTROLregister. ANDR0,R0,#&FBClearbitKEN STRBR0,[R1,#3]todisablekeyboardinterrupts. MOVR0,#1SetEOLflag. STRR0,EOL LDMFDR13!,{R0-R2,R14}Restoreregisters SUBSPC,R14irq,#4andreturn. Figure 4.13. An ARM interrupt-service routine to read an input line from a keyboard based on Figure 4.9.

7. DATAIN 1 SIN Ready A31 A1 A0 Address decoder D7 D0 R/W Figure 4.33. Combined input/output interface circuit. A2 DATAOUT Input status Bus PA7 PA0 CA PB7 PB0 CB1 CB2 SOUT D1 RS1 RS0 My-address Handshake control Master- Ready Slave-

9. Handshake control DATAOUT Printer data Idle Valid Read Load SOUT ready A31 A1 A0 Address decoder D 7 Q 7 D 0 Q 0 D7 D0 Figure 4.35.A parallel point interface for the bus of Figure 4.25, with a state-diagram for the timing logic. statusdata D 1 Q 1 D0 Timing Logic Clock My-address R/W Slave- Idle Respond My-address Go Go=1

11. memory Processor Bridge Processor bus PCI bus Main memory Additional controller CD-ROM controller Disk Disk 1Disk 2 ROM CD- SCSI controller USB controller Video KeyboardGame disk IDE SCSI bus Figure 4.38. An example of a computer system using different interface standards. ISA interface Ethernet interface

12. Host computer Root hub Hub Figure 4.43. Universal Serial Bus tree structure. I/O device Hub I/O device I/O device Hub I/O device I/O device I/O device

13. Host computer Root Hub Hub A Device Figure 4.44. Split bus operation D F/LS HS - High speed F/LS- Full/Low speed Hub B Device C

14. PID 0 1 2 3 0 0 1 2 3 (a) Packet identifier field PIDADDRENDPCRC16 8745Bits (b) Token packet, IN or OUT PIDDATACRC16 80 to 819216Bits (c) Data packet Figure 4.45. USB packet format.

16. PIDFrame numberCRC5 8115Bits (a) SOF Packet Figure 4.47. USB frames. ST3DS 1-ms frame T7DT3D S- Start-of-frame packet Tn- Token packet, address = n D- Data packet A- ACK packet (b) Frame example

17. Table 4.4 The SCSI bus signals. CategoryNameFunction DataDB(0)to DB(7) Datalines:Carryonebyteofinformation duringtheinformationtransferphaseand identifydeviceduringarbitration,selectionand reselectionphases DB(P)Paritybitforthedatabus PhaseBSYBusy:Assertedwhenthebusisnotfree SELSelection:Assertedduringselectionand reselection Information type C/DControl/Data:Assertedduringtransferof controlinformation(command,statusor message) MSGMessage:indicatesthattheinformationbeing transferredisamessage HandshakeREQRequest:Assertedbyatargettorequestadata transfercycle A CKAcknowledge:Assertedbytheinitiatorwhenit hascompletedadatatransferoperation Directionof transfer I/OInput/Output:Assertedtoindicateaninput operation(relativ e totheinitiator) Other A TNAttention:Assertedbyaninitiatorwhenit wishestosendamessagetoatarget RSTReset:Causesalldevicecontrolstodisconnect fromthebusandassumetheirstart-upstate – – – – – – – – – – – –