1. 27 October 2015 Birkbeck College, U. London1 Introduction to Computer Systems Lecturer: Steve Maybank Department of Computer Science and Information Systems sjmaybank@dcs.bbk.ac.uk Autumn 2015 Week 5b: Types of Instruction

2. 27 October 2015 Brookshear, Section 2.22 Machine Architecture Address | Cells 00 01.... FF Arithmetic/ logic unit Registers.... 0 F 1 Program counter Instruction register Bus Main memory Central processing unit Control unit

3. 27 October 2015 Brookshear, Section 2.23 Machine Language Concepts Registers (R, S, T…) Memory addresses Number of bytes in a memory cell Instruction Sequence of instructions Branching (choice of next instruction)

4. Properties of the Illustrative Machine No. memory cells: 256 No. bits in a memory cell: 8 (1 byte) No. registers: 16 No. bits in a register: 8 (1 byte) No. bits in the programme counter: 8 (1 byte) No. bits in the instruction register: 16 (2 bytes) 27 October 2015 Birkbeck College, U. London4

5. 27 October 2015 Brookshear, Appendix C5 Illustrative Machine Language Op-codeOperanddescription 1RXYLOAD R from memory location XY 2RXYLOAD R with the bit pattern XY 3RXYSTORE R at memory location XY 40RSMove bit pattern in R to S 5RSTAdd (2s comp) contents of S,T. Put result in R 6RSTAdd (fp) contents of S,T.Put result in R

6. 27 October 2015 Brookshear, Appendix C6 Illustrative Machine Language Op-codeOperandDescription 7RSTOR contents of S, T. Put result in R 8RSTAND contents of S, T. Put result in R 9RSTXOR contents of S, T. Put result in R AR0XRotate right contents of R for X times. BRXYIf contents R=contents register 0, then jump to instruction at address XY, otherwise continue as normal. C000Halt

7. 27 October 2015 Brookshear, Section 2.27 Types of Instruction Data transfer LOAD, STORE, MOVE Arithmetic/Logic ADD, OR, AND, XOR, ROTATE Control JUMP, HALT

8. 27 October 2015 Brookshear, Section 2.28 Format of an Instruction Instruction=op-code field+operand field Op-code: identifies the elementary operation, e.g. STORE, SHIFT, XOR, JUMP. Operand: additional information, e.g. data or a register address.

9. 27 October 2015 Brookshear, Section 2.39 Instruction 156C 156C Op-code 1: load Register with bit pattern in memory at the given address register memory address

10. 27 October 2015 Brookshear, Section 2.310 Op Code 7 (OR) 10011101 00010111 10011111 1 st register 2 nd register 3 rd register OR =

11. 27 October 2015 Brookshear, Section 2.311 Op Code A (Rotate right) 10011101 11001110 01100111 register rotate right 1 rotate right 2

12. 27 October 2015 Brookshear, Section 2.312 Instruction B258 B258 Op-code B: change value of program counter if contents of indicated register = contents of register 0 Indicated register New contents of program counter Brookshear, Fig. 2.9.

13. Translate into Machine Language 1. Load register number 3 with the hexadecimal value 56 2. Rotate register number 5 three bits to the right 3. AND the contents of register A with the contents of register 5 and leave the result in register 0 25 October 2015 Brookshear, Section 2.213

14. Brookshear, Section 2.314 Machine Cycle Fetch next instruction from memory to the CPU Decode the instruction Execute the instruction 27 October 2015 Fetch Decode Execute

15. 27 October 2015 Brookshear, Section 2.315 First Part of the Fetch Step of the Machine Cycle bus CPU Main memory program counter A0 instruction register 156C addresscells A0 A1 A2 A3 15 6C 16 6D

16. 27 October 2015 Brookshear, Section 2.316 Completion of the Fetch Step bus CPU Main memory program counter A2 instruction register 156C addresscells A0 A1 A2 A3 15 6C 16 6D

17. 27 October 2015 Brookshear, Section 2.317 Updating the Program Counter Fixed length instructions (2 bytes). Instructions stored consecutively in main memory. Each memory cell holds 1 byte. Then pc  pc + 2 at the end of each Fetch. … 5 6 7 8 9 10 11 12 13 14 … pc=7 memory

18. Example The machine is started with 00 in the program counter. Describe the actions of the CPU if the memory contains the following bit patterns. 27 October 2015 Brookshire, Section 2.318 Address Contents 0014 0102 34 0317 04C0 0500

19. 27 October 2015 Brookshear, Section 2.319 Program to Add Two Values 1. Get the first value from memory and place it in a register S. 2. Get the second value from memory and place it in another register T. 3. Add the contents of S, T and place the result in a register R. 4. Store the result in R in memory 5. Stop

20. 27 October 2015 Brookshear, Section 2.320 Encoded Program 1. 156C. Load register 5 with the contents of memory cell 6C. 2. 166D. Load register 6 with the contents of memory cell 6D 3. 5056. Add (2s comp) contents of registers 5, 6. Put result in register 0. 4. 306E. Store the contents of Register 0 at memory cell 6E. 5. C000. Halt.

21. 27 October 2015 Birkbeck College, U. London21 Without Instruction B  A program containing n instructions would run for n-1 machine cycles.  The program would be unable to respond to changes in the data.

22. 27 October 2015 Birkbeck College, U. London22 Fibonacci Numbers  0,1,1,2,3,5,8,13,21,34,55, …  N(1)=0, N(2)=1  N(i+1)=N(i)+N(i-1) for i=2,3,4, …

23. 27 October 2015 Birkbeck College, U. London23 Program to Find the 10 th Fibonacci Number 20 2000 // load register 0 with 0 22 2100 // load register 1 with 0 24 2201 // load register 2 with 1 26 2408 // load register 4 with 8 28 25FF // load register 5 with -1 (Two’s Comp) Address Instruction Comment R0 R2 R3 R4 R1 R5 00 08 ** 01 00 FF

24. 27 October 2015 Birkbeck College, U. London24 Program to Find the 10 th Fibonacci Number 2A 5312 // Add contents of R1, R2. Put result in R3 3C 4021 // Move bit pattern in R2 to R1 2E 4032 // Move bit pattern in R3 to R2 30 5445 // Add contents of R4, R5. Put result in R4 32 B436 // If contents R4=contents R0, go to 36 34 B02A // If contents R0=contents R0, go to 2A 36 C000 // Halt. Result is in R2. Address Instruction Comment

25. 27 October 2015 Brookshear, Section 6.125 Assembly Language Mnemonic system for representing machine language Machine language 156C 166D 5056 306E C000 Assembly language LD R5, Price LD R6, ShippingCharge ADDI R0, R5, R6 St R0, TotalCost HLT