1. L10 : Lower Power High Level Synthesis(1) 1999. 8 성균관대학교 조 준 동 교수 http://vada.skku.ac.kr

2. Low Power Design Flow

3. Early Analysis Leads to Power Savings National Semiconductor Success A LAN switch ASIC of 200K gates and 41 memories characterized for state-dependent power. DesignPower revealed excessive power consumption by the memories due to redundant read cycles. The RTL was fixed and the power consumption reduced

4. Module Selection Select the clock period, choose proper hardware modules for all operations(e.g., Wallace or Booth Multiplier), determine where to pipeline (or where to put registers), such that a minimal hardware cost is obtained under given timing and throughput constraints. Full pipelining: ineffective clock period mismatches between the execution times of the operators. performing operations in sequence without immediate buffering can result in a reduction of the critical path. Clustering operations into non-pipelining hardware modules, the reusability of these modules over the complete computational graph be maximized. During clustering, more expensive but faster hardware may be swapped in for operations on the critical path if the clustering violates timing constraints

5. High-Level Power Estimation P core = P DP + P MEM + P CNTR + P PROC P DP = P REG +P MUX +P FU + +P FU, where P REG is the power of the registers P MUX is the power of multiplexers P FU is the power of functional units P INT is the power of physical interconnet capacitance

6. Estimation Estimate min and max bounds on the required resources to – delimit the design space min bounds to serve as an initial solution – serve as entries in a resource utilization table which guides the transformation, assignment and scheduling operations Max bound on execution time is t max : topological ordering of DFG using ASAP and ALAP Minimum bounds on the number of resources for each resource class Where N Ri : the number of resources of class R i d Ri : the duration of a single operation O Ri : the number of operations

7. High-Level Power Estimation: P REG Compute the lifetimes of all the variables in the given VHDL code. Represent the lifetime of each variable as a vertical line from statement i through statement i + n in the column j reserved for the corresponding varibale v j. Determine the maximum number N of overlapping lifetimes computing the maximum number of vertical lines intersecting with any horizontal cut-line. Estimate the minimal number of N of set of registers necessary to implement the code by using register sharing. Register sharing has to be applied whenever a group of variables, with the same bit-width b i. Select a possible mapping of variables into registers by using register sharing Compute the number w i of write to the variables mapped to the same set of registers. Estimate n i of each set of register dividing w i by the number of statements S: i =w i /S; hence TR imax = n i f clk. Power of latches and flip flops is consumed not only during output transitions, but also during all clock edges by the internal clock buffers The non-switching power P NSK dissipated by internal clock buffers accounts for 30% of the average power for the 0.38-micron and 3.3 V operating system. In total,

8. P CNTR After scheduling, the control is defined and optimized by the hardware mapper and further by the logic synthesis process before mapping to layout. Like interconnect, therefore, the control needs to be estimated statistically. Global control model: Local control model: the local controller account for a larger percentage of the total capacitance than the global controller. Where Ntrans is the number of tansitions, nstates is the number of states, Bf is the bus factor, and Clc is the capacitance switched in any local controller in one sample period. Bf is the ratio of the number of bus accesses to the number of busses.

9. N trans The number of transitions depends on assignment, scheduling, optimizations, logic optimization, the standard cell library used, the amount of glitchings and the statistics of the inputs.

10. Exploring the Design Space Find the minimal area solution constrained to the timing constraints By checking the critical paths, it determine if the proposed graph violates the timing constraints. If so, retiming, pipelining and tree height reduction can be applied. After acceptable graph is obtained, the resource allocation process is initiated. – change the available hardware (FU's, registers, busses) –redistribute the time allocation over the sub-graphs –transform the graph to reduce the hardware requirements. Use a rejectionless probabilistic iterative search technique (a variant of Simulated Annealing), where moves are always accepted. This approach reduces computational complexity and gives faster convergence.

11. Behavioral Synthesis loop unrolling : localize the data to reduce the activity of the inputs of the functional units or two output samples are computed in parallel based on two input samples. Neither the capacitance switched nor the voltage is altered. However, loop unrolling enables several other transformations (distributivity, constant propagation, and pipelining). After distributivity and constant propagation, The transformation yields critical path of 3, thus voltage can be dropped. Clock Selection : Choose optimal system clock period Eliminate slacks/improve resource utilization and Enable greater voltage scaling Module selection : For each operation, choose library template Flow graph restructuring : pull out operations on the critical cycle.

12. High-Level Power Estimation: P MUX and P FU

13. Critical Path Longest delayed path from input to output in combinational logic Determine operating clock frequency Resizing non-critical path transistor (In-Place Optimization) Critical path in Synchronous Sequential logic

14. Data path Synthesis

15. System Partitioning To decide which components of the system will be realized in hardware and which will be implemented in software High-quality partitioning is critical in high-level synthesis. To be useful, high- level synthesis algorithms should be able to handle very large systems. Typically, designers partition high-level design specifications manually into procedures, each of which is then synthesized individually. Different partitionings of the high-level specifications may produce substantial differences in the resulting IC chip areas and overall system performance. To decide whether the system functions are distributed or not. Distributed processors, memories and controllers can lead to significant power savings. The drawback is the increase in area. E.g., a non- distributed and a distributed design of a vector quantizer.

16. Circuit Partitioning graph and physical representation

17. VHDL example process communication control/data flow graph Behavioral description

18. Clustering Example Two-cluster Partition Three-cluster Partition

19. Clustering (Cont’d)

20. - 설계 자동화 연구실 - 상위 수준 합성 단계

21. - 설계 자동화 연구실 - ( High Level Synthesis ) 상위 수준 합성 ( High Level Synthesis ) Instructions Operations Variables Arrays signals 회로의 동작적 기술 Control Datapath Memory Operators, Registers, Memory, Multiplexor Control scheduling Memory inferencing Register sharing Control interencing for(I=0;I<=2;I=I+1begin @(posedge clk); if(fgb[I]%8; begin p=rgb[I]%8; g=filter(x,y)*8; end............ constraints RTL(register transfer level) architecture 상위 수준 합성

22. High-Level Synthesis The allocation task determines the type and quantity of resources used in the RTL design. It also determines the clocking scheme, memory hierarchy and pipelining style. To perform the required trade-offs, the allocation task must determine the exact area and performance values. The scheduling task schedules operations and memory references into clock cycles. If the number of clock cycles is a constraint, the scheduler has to produce a design with the fewest functional units The binding task assigns operations and memory references within each clock cycle to available hardware units. A resource can be shared by different operations if they are mutually exclusive, i.e. they will never execute simultaneously.

23. - 설계 자동화 연구실 - 상위 수준 합성 과정 예

24. Low Power Scheduling

25. - 설계 자동화 연구실 - 상위 레벨에서 제안된 저전력 방법 Sibling 연산의 연산자 공유 [ Fang, 96 ] 데이타 correlation 를 고려한 resource sharing [ Gebotys, 97 ] FU 의 shut down 방법 ( Demand-driven operation ) [ Alidina, 94 ] 연산의 규칙성 이용 [ Rabaey, 96 ] Dual 전압 사용 [ Sarrafzadeh, 96 ] Spurious 연산의 최소화 [ Hwang, 96 ] 최소 비용의 흐름 알고리즘을 사용한 스위칭 동작 최소화 + 연결구조 단순화를 통한 캐패시턴스 최소화 [Cho,97]

26. - 설계 자동화 연구실 - 레지스터의 전력 소모 모델 Power(Register) = switching(x)(C out, Mux +C in,Register )+switching(y) x (C out, Register +C in, DeMux ) switching(x)=switching(y) 이므로 Power(Register)=switching(y) x C total

27. - 설계 자동화 연구실 - CDFG( control data flow graph ) +1 +2 +3 *1 ab cd e g f h e=a+b; g=c+d; f=e+b; h=f*g; 회로의 CDFG 표현

28. Schematic to CDFG of FIR3

29. - 설계 자동화 연구실 - 레지스터와 리소스의 수 결정 adcbefgh 1 2 3 4