1. WP2: On Detector Systems 2.1 Strip Sensors Layout Evaluation 2.2 ASICs Digital Design Evaluation Wafer Test 2.3 Hybrids Layout & Manufacture Die Attach Tooling Evaluation Skill Transfer 2.4 Modules Build Process & Tooling Evaluation Skill Transfer 2.6 On-Stave Interface Design Evaluation 2.5 Tapes Layout & Manufacture Flying Probe Machine Evaluation Delivers Sensors, ASICs and Hybrids to the Module programme; Modules, Tapes and On-Stave Interfaces to the Stavelet and Stave programmes ABCN-25 BCC Picture shows Serially Powered Stavelet 1

2. WP 2.1 Strip Sensors Original plan: next strip sensor procurement would be to suit 130nm chipset – May now need to procure a few tens of sensors for 250nm chipset... ATLAS07 Sensors for modules with ABCN-25 chips were made on two substrate materials: – FZ-1 (~6.7kohm cm) – FZ-2 (~6.2kohm cm) FZ-1 sensors generally have lower leakage current than FZ-2 sensors – First stavelet uses 3 FZ-2 sensors and 1 FZ-1 sensor – Later stavelets and stave were foreseen to use only FZ-1 sensors After module assembly, FZ-1 sensors have been seen to develop reduced breakdown voltages (micro-discharge) – Observed with UK stave modules Hybrids glued to sensor face – Also seen with KEK/Geneva double sided designs Nothing touches the sensor face (hybrids are bridged) – Reproduced at UCSC using sensor held under intermittent vacuum Physical deformation is temporary but IV degradation is permanent 2

3. WP 2.1 Strip Sensors IR Microscopy of Damaged Sensor Y Unno, KEK IR images of affected sensors show problem at edge of guard ring – Assembly stresses may cause damage to the SiO 2 passivation in this region Studies continue – IR microscopy of affected sensors will be performed in Japan Likely fix – More robust SiO 2 passivation – May require validation studies / irradiation How does this affect WP2? – Short term: build stavelets using FZ-2 sensors – Medium term: may need to buy 5-10 sensors for the validation study, and then to replace all FZ-1 sensors needed for Stave 250 programme  As 130nm chipset is delayed wrt the original schedule, this can be funded within the existing WP2 programme. X10 IR, Bias~400 V, ~10 µA Hot spots 3

4. WP2.2 ASICs: 250nm chipset Final 4 ABCN-25 wafers to be screened in UK – Work split between RAL and Glasgow skill transfer between institutes: both sites would participate in any production screening – 3 screened at RAL – 1 + 1 to be screened at Glasgow Dicing to be performed in UK industry (Micross) 4 Wafer A5GJ0HX Preliminary Result

5. WP2.2 ASICs: 130nm chipset First 130nm Test Structures back – PCBs to test Serial Powering Protection elements being assembled at RAL Many aspects of ABCN-13 baseline specification now agreed – 256 channel chip – 2 stage triggering - L0, L1 to allow trigger latencies of >100us – Regional readout track trigger functions to be included Recent work has focussed on trigger architecture and data format – Simulations performed in UK to assess data format and compression algorithms Addition of TD ASIC designer to the Hybrid Controller Chip (HCC) team much appreciated by the community – Was previously under resourced Submission Target still Q1/Q2 2012 5 SEU Logic partSPP Elements First 130nm Test Structures

6. WP2.3 Hybrids Circuits made by Stevenage Circuits 120 circuits ordered late 2010 – First delivery: 106 rejects Poor quality gold plating Useful for mechanical assemblies Retained at discounted price – Second Delivery: 100 good circuits Sufficient for medium term Passives added by Hawk Electronics 39 of latest batch populated – Best solder quality to date – 7 circuits inspected and metrologised using SmartScope 2 ASIC populated – ready for next UK module 5 sent to UCSC – Will mount their own ASICs 6

7. WP2.4 Modules: Gluing Studies Gluing studies finished and now getting consistent glue thicknesses 5 modules have been assembled with new gluing techniques. -Now glue uniformity limited to flatness of incoming hybrids Of the 5 modules 2 are ready for DC/DC stave 1 is ready for testing 1 is being bonded (FZ1 with breakdown at 270 V) 1 needed hybrid debugging (assembled with untested hybrids with bonding problems) 7

8. Impact of Glue thickness on Module Performance Input Noise at 1fC 588e 599e Input Noise at 1fC 590e 599e AC Inner AC Outer AC Inner AC Outer DC Inner DC Outer DC Inner DC Outer Input Noise at 1fC 605e 647e Input Noise at 1fC 584e 634e Module with thick glue layerModule with normal glue layer 32 microns 15 microns 57 microns 25 microns 143 microns 102 microns 101 microns 94 microns 8

9. WP2.4 Modules: Gluing Flatness Module 15Module 16 Module 13 Module 14 9

10. Hybrid and Module Production Roll-out 6 sites are now actively pursuing gluing trials of hybrids and/or modules LBL,UCSC, Cambridge, Liverpool, DESY, Freiburg Glasgow is beginning to plan on making a set of jigs for themselves Freiburg and Glasgow are coming to Liverpool for training session May 17-18 th UCSC is bonding/testing first hybrid now Cambridge has already bonded/tested first hybrids SP Module in Test Frame 10

11. Modules: Double Trigger Noise The Double Trigger Noise test sends two triggers to a module or stave(let) with controlled, variable spacing, keeping the ASICs at fixed threshold – The trigger spacing is varied to scan for noise correlated with trigger or readout activity. The test has been applied to stave modules powered in three ways: – Serially Powered – Parallel Powered – Powered through individual DC-DC convertors In all cases, a small dV is observed on the power rails correlated with the reception of trigger commands or configuration data – Maybe specific to ABCN-25 chipset? 11 Stavelet Hybrid 7, BWL ON 150nS = 6 BCO COM DATA dV

12. Modules: Double Trigger Noise For a serially powered module running at 1fC threshold, increased occupancy is observed at certain timings on one hybrid of the pair – The time profile fits with the dV signal – The effect spreading to the other hybrid as the threshold is lowered For parallel powered modules or those with DC-DC convertors, the effect is seen at very low thresholds – Well below expected 0.7fC operating point For SP modules, the dV signal is being picked up in the front end – This is most likely due to the way the two hybrids are referenced in the SP module 12 Serially Powered Module, DTN at 1fC threshold Channel Time 6 BCO = 150nS

13. Modules: Double Trigger Noise Tests continue to determine ways to reduce this effect – Reducing the inductance of referencing ties helps – Extra decoupling of the power rails can help What does this mean? – Optimistic: need to improve referencing – Pessimistic: reduce powering modularity from n hybrids to n/2 modules Places both hybrids at same DC potential wrt sensor What does this mean for WP2? – PCBs to permit reduced modularity operation of existing stavelet will be ordered this week – Modules and Tapes for a second SP stavelet will not be built until this issue has been resolved 13

14. WP2.5 Tapes: Shield Optimisation Work underway to determine material needed to screen the detector backplane from aggressor signals on the bus tape – Potential for mass reduction Image shows a single module mounted above a shielded test tape – Basic noise results agree with expectation – Injection studies just beginning Shield Optimisation Studies 14

15. WP2.5 Tapes: Production and QA Power tape for DC-DC stavelet – Successfully made in house at Oxford – Mounted onto a stavelet core at LBNL – Modules to be added shortly at RAL Flying probe / visual inspection system is being made – An order for a computer controlled gantry system had to be cancelled as the vendor refused to deliver what their sales team had promised! Will submit replacement order to a different vendor – A camera/capture system has been procured DC-DC Power Tape 15

16. WP2.6 On Stave Interface The present End Of Stave board implements an electrical interface between the stave(let) and the off-detector electronics – Its performance is satisfactory – We plan to use the existing board for all stave(let)s using ABCN-25 Final staves using the ABCN-13 chipset will instead use a high bandwidth optical link using the GBT GigaBit Transceiver protocol running over the VL Versatile Link – This work package follows developments within the GBT and VL projects to ensure their compatibility with the ABCN-13 chipset, leading toward the implementation of a suitable End Of Stave board The international community is making good progress! – Whilst FPGA-based demonstrator systems are available, given present funding constraints in the UK we do not immediately plan to procure such a system Meanwhile the UK’s contribution to optical links for the ATLAS tracker upgrade is focussed upon the characterisation of passive optical components as part of the VL collaboration (see WP3) 16

17. WP2: Deliverables and Key Notes DeliverableTargetStatus Modules for DC-DC Stavelet03/1150% Complete. 2 ready, 1 pending test, 1 being bonding, 1 requires hybrid debugging. Expect completion 05/11. Probe last 4 ABCN-25 Wafers04/1175% Complete. Expect completion 05/11. Modules for SP Stavelet05/11Second SP stavelet delayed pending double trigger noise studies. Key Progress Optimisation of module glue layer Reduced module noise Roll-out of hybrid and module assembly to multiple institutes Skill Transfer UK and Overseas Key Issues Breakdown of FZ1 sensors May need to be replaced Double Trigger Noise on SP modules Resolution may involve changes to tape design, extra decoupling and/or revised module hook-up 17

18. Backup 18

19. Stavelet Core (WP4) DC-DC Power Tape (WP2) Misc. Support PCBs (WP2, not shown) Construction of 4 modules in progress (WP2) Module (WP2) Cu Plated Shield (WP3) DC-DC convertors (CERN) Custom Module Frame PCB (WP2) Results in agreement with SP module provided adequate shielding used WP2: Recent Deliverables For the DC-DC Stavelet DETAIL First DC-DC Test of Stave ModuleFirst DC-DC Stavelet 19