1. Microprocessor system architectures – IA32 paging Jakub Yaghob

2. Control – global setting PGPagingCR0[31] PDBRPage Directory Base RegisterCR3 Page Fault Linear AddressCR2 PSEPage Size ExtensionsCR4[4]Pentium+ PAEPhysical Address ExtensionsCR4[5]Pentium Pro+ CDCache DisableCR0[30]i486+ NWNot Write-throughCR0[29]i486+ WPWrite ProtectCR0[16]Pentium+ PGEPage Global EnableCR4[7]Pentium Pro+ PCIDProcess-context identifierCR4[17]Haswell PCDPage-level Cache DisableCR3[4]i486+ PWTPage-level Writes TransparentCR3[3]i486+

3. Paging modes PGPAEPSE PS (PDE) PSE-36 (CPUID) Page size Physical adress size 0XXXX-Paging disabled 100XX4 KB32 1010X4 KB32 101104 MB32 101114 MB36 11X0X4 KB36 11X1X2 MB36

4. Address translation – 4K pages, 32-bit physical address

5. Address translation – 4M pages, 32-bit physical address

6. Page Directory – 4K/32b

7. Page Table – 4K/32b

8. Page Directory – 4M/32b

9. PAE – Page Address Extension Widens possibility of addressing physical memory to 36 bits (64GB) Available from Pentium Pro Paging data structures changed Other release of OS (different compilation) PDBR changed Bit NX (No eXecute)/XD (eXecution Disabled) Newer AMD/Pentium 4

10. Address translation – 4K pages, 36-bit physical address

11. Address translation – 2M pages, 36-bit physical address

12. Page table entries – 4K/36b

13. Page table entries – 2M/36b

14. PSE-36 – Page Size Extension 36-bit An alternate method to the PAE Allows addressing of 36 bits physical address space using 4M pages Available from Pentium III Only when PSE-36 flag available (CPUID[17])

15. Address translation – 4M pages, 36-bit physical address

16. Page Directory – 4M/36b

17. Page fault All paging problems caught by #PF exception Flag P set to 0 Access rights violation Page table or page directory

18. Protection U/S flag =0 – supervisor mode CPL 0-2 =1 – user mode CPL 3 R/W flag =0 – read-only Not used in supervisor mode, until flag WP (CR0[16]) is set =1 – read/write NX/XD flag =0 – can execute =1 – no execute

19. TLB – Translation Lookaside Buffer Associative memory for accelerating translation from linear to physical address TLB purging Explicitly using mov cr3, eax Implicitly during task change – reading new CR3 Entries with G flag set are not purged when PGE is set (CR4[7]) Selective entry purging Instruction INVLPG

20. Process-context ID Cache information for multiple linear-address spaces 12-bit ID Enabled by CR4.PCIDE=1 Bits CR3[11:0] Bits PCD, PWT treated as 0 TLB entries widened with PCID TLB translation only for current PCID

21. PAE in long mode Max limits 64-bit linear address 52-bit physical address Current implementation 48-bit linear address 40-bit physical address Setting PAE must be enabled before switching to long mode

22. Address translation – 4K pages in long mode

23. Address translation – 2M pages in long mode

24. Page table entries – 4K/long mode – I

25. Page table entries – 4K/long mode – II

26. Page table entries – 2M/long mode