1. Hall–D Level-1 Trigger Commissioning Part II A.Somov, H.Dong Jefferson Lab 12 GeV Trigger Workshop, July 8, 2010  Play Back Test Vector in Hall-D commissioning  Hall-D member commissioning responsibilities  Single crate Trigger Test Stand. Test Vector implementation  Future plans

2. Play Back Test Vector in Hall-D Commissioning Hall-D Level-1 Trigger Commissioning, 12 GeV Trigger Workshop at CNU, July 08, 2010 2 Use Test Vector to check hardware performance:  Load predefined data amplitudes (patterns) corresponding to specific trigger types (cosmics, physics, …) to FADC250 memory. Verify triggers produced by electronics.  Load signal amplitudes taken from Geant to the FADC250’s and compare the trigger output with the Level-1 bit-wise simulation.  Test/debug performance of online monitors (scalers).

3. Hall-D Trigger Commissioning Responsibilities Level-1 Trigger Control Lelev-1 Online Monitor Data Quality Monitor Board Control Board Initialization Load FPGA, Load Test Vector samples CODA FADC 250 cMsg DBRun Control SD TI CTP ROC FADC 250 Crate trigger type & data to TS crate Software to be developed by Hall-D members Play Back Test Vector implementation Hall-D Level-1 Trigger Commissioning, 12 GeV Trigger Workshop at CNU, July 08, 2010 3

4. Trigger Test Stand Pulse Generator TIFADCROCK Discriminator Delay Trig IN Trigger Trig INTrig OUT VME Play Back - CODA - Load Samples Load signal pulse amplitudes (data samples) to the FADC FPGA memory Use external pulse generator - for the trigger interrupt (initiate FADC VME readout) - to send Play Back signal to the FADC through the VME P2 bus. Play Back pulse width defined how many data samples to process Readout pulse shapes using CODA - check FADC readout modes: Window Raw Data (data samples for the trigger window), Pulse Raw Data (data samples around the ADC threshold), Pulse Integral (energy sum) Hall-D Level-1 Trigger Commissioning, 12 GeV Trigger Workshop at CNU, July 08, 2010 4

5. Trigger Test Stand Play Back pulse Readout Window Hall-D Level-1 Trigger Commissioning, 12 GeV Trigger Workshop at CNU, July 08, 2010 5 Amplitudes loaded to FADC250 FPGA Different pulse shapes can be loaded to each of 16 FADC channels - the memory size of each channel corresponds to 32 data samples x 4 ns = 128 ns FADC was operated in the Window Raw Data mode, i.e., readout out specific number of data samples The Play Back pulse width ~130 ns

6. Summary / Future Plans  The play back mode has been implemented and tested using the single crate Test Stand - different signal shapes can be loaded to each FADC channels  Level-1 trigger bit-wise simulation is currently under development  We have started preparing online software for the Level-1 trigger commissioning  We are waiting for more electronics boards and “official” DAQ software for them. The two crate test stand will hopefully be ready by the end of this year Hall-D Level-1 Trigger Commissioning, 12 GeV Trigger Workshop at CNU, July 08, 2010 6

7. Test Vector Implementation  Load FADC amplitudes of signal pulses to FPGA’s memory.  Trigger Supervisor initiates processing of the samples through the trigger hardware. Play Back signal will be delivered to the FADC through one of the trigger lines. 16 ch 1 - 16 FADC FADC TS SSP GTP CTP SD TI SD TD Play Back Trigger 1 - 8 Hai Dong Ed Jastrzembski David Abbott Ben Rayado Alex Somov

8. Play Back Mode: FADC LX25 FX20  Altera FPGA FIFO CTP VMEbus Self Trigger Load Samples to Memory Play Back Trig from TI (one line for play back)  Load amplitudes of signal pulses (samples) to FPGA memory.  Play Back pulse width defines how many samples to process.  Trigger from TI initiates the VME readout (trigger can also be initiated by FX20 – self trigger mode) play back pulse pulse in the memory 16 x 4 ns = 64 ns (currently) Current version of FADC250